Regviz

Freescale Semiconductor /MK70F12 /DMAMUX1 /CHCFG14

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CHCFG14

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MK70F12/DMAMUX1/CHCFG14#0x0

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)SOURCE0 (0)TRIG 0 (0)ENBL

TRIG=0, SOURCE=0, ENBL=0

Description

Channel Configuration Register

Fields

SOURCE

DMA Channel Source (slot)

0 (0): Disable_Signal

2 (2): UART0_Rx_Signal

3 (3): UART0_Tx_Signal

4 (4): UART1_Rx_Signal

5 (5): UART1_Tx_Signal

6 (6): UART2_Rx_Signal

7 (7): UART2_Tx_Signal

8 (8): UART3_Rx_Signal

9 (9): UART3_Tx_Signal

10 (10): UART4_Rx_Signal

11 (11): UART4_Tx_Signal

12 (12): UART5_Rx_Signal

13 (13): UART5_Tx_Signal

14 (14): I2S0_Rx_Signal

15 (15): I2S0_Tx_Signal

16 (16): SPI0_Rx_Signal

17 (17): SPI0_Tx_Signal

18 (18): SPI1_Rx_Signal

19 (19): SPI1_Tx_Signal

20 (20): SPI2_Rx_Signal

21 (21): SPI2_Tx_Signal

22 (22): I2C0_Signal

23 (23): I2C1_Signal

24 (24): FTM0_Channel0_Signal

25 (25): FTM0_Channel1_Signal

26 (26): FTM0_Channel2_Signal

27 (27): FTM0_Channel3_Signal

28 (28): FTM0_Channel4_Signal

29 (29): FTM0_Channel5_Signal

30 (30): FTM0_Channel6_Signal

31 (31): FTM0_Channel7_Signal

32 (32): FTM1_Channel0_Signal

33 (33): FTM1_Channel1_Signal

34 (34): FTM2_Channel0_Signal

35 (35): FTM2_Channel1_Signal

40 (40): ADC0_Signal

41 (41): ADC1_Signal

42 (42): CMP0_Signal

43 (43): CMP1_Signal

44 (44): CMP2_Signal

45 (45): DAC0_Signal

46 (46): DAC1_Signal

47 (47): CMT_Signal

48 (48): PDB0_Signal

49 (49): PORTA_Signal

50 (50): PORTB_Signal

51 (51): PORTC_Signal

52 (52): PORTD_Signal

53 (53): PORTE_Signal
TRIG

DMA Channel Trigger Enable

0 (0): Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode)

1 (1): Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode.
ENBL

DMA Channel Enable

0 (0): DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

1 (1): DMA channel is enabled

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data